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dc.contributor.authorLin, TCen_US
dc.contributor.authorLee, KBen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:26:16Z-
dc.date.available2014-12-08T15:26:16Z-
dc.date.issued2003en_US
dc.identifier.isbn0-7803-7795-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/18661-
dc.description.abstractThe ongoing advancements in VLSI technology allow SoC design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient memory controller that contains a quality-aware scheduler and a configurable DRAM memory interface socket to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Simulation results show that the latency of the latency-sensitive data flow can be reduced to 50%, and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control.en_US
dc.language.isoen_USen_US
dc.titleQuality-aware memory controller for multimedia platform SOCen_US
dc.typeProceedings Paperen_US
dc.identifier.journalSIPS 2003: IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATIONen_US
dc.citation.spage328en_US
dc.citation.epage333en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000188174000061-
Appears in Collections:Conferences Paper