應用於多媒體系統單晶片平台之多層式記憶體控制器

Abstract

由於積體電路在製程上不斷的進步，因此在以IC為核心的產品裡，增加了許多發展的機會，可以將各種不同特質的控制與運算功能模組整合在單晶片系統。而佔一個系統最大面積與功率消耗的部份，往往就是記憶體與記憶體的存取，目前這部份主要仍是以晶外記憶體，特別是同步隨機動態存取記憶體(SDRAM)，來實現。SDRAM雖有密度高、成本較低的優點，但由於其內部管線式(pipeline)與記憶體庫(memory bank)的架構設計，造成一般的SDRAM記憶體控制器，無法有效使用記憶體本身所能提供的最大頻寬。另一方面，由於功能模組對記憶體使用的需求不同，如必須保證某些功能模組頻寬的取得或讓存取延遲（latency）越短越好等，一般通用型記憶體控制器並無法有效滿足每個功能模組不同的需要。 針對上述的問題，本論文提出了一個適合於多媒體單晶片系統的分層式SDRAM記憶體控制器。此分層式SDRAM控制器的第零層為一高效率且可程式化及可配置化的SDRAM記憶體介面插槽，能讓系統設計者快速地整合SDRAM晶外記憶體子系統至所應用的設計中。搭配第一層—品質感測排程器—此記憶體控制器亦有能力根據不同功能模組對記憶體的使用需求，提供最小存取延遲與保證頻寬兩種服務，進而達到保證服務品質的目標。此外，針對多媒體運算單元所設計的第二層—記憶體存取位址產生器—能夠有效地減少位址匯流排上的傳輸次數，而增進晶內匯流排的傳輸效率。另一方面，本記憶體控制器的多層式設計能夠讓系統設計者依據其記憶體使用需求，整合最適用的層級功能。在模擬機上盒環境的效能評估中，相較於傳統的多通道記憶體控制器，我們所設計的多層式控制器的保證頻寬服務可以精準的分配記憶體頻寬給各功能模組，而最小存取延遲服務也可以減少37%~65%的存取延遲。

The ongoing advancements in VLSI technology allow SoC design to integrate heterogeneous control and computing functional units into a single chip. In such systems, memories and memory accesses often occupy the largest area and consume the most power consumption respectively. Therefore, the pressure of area and cost leads to a single, shared off-chip DRAM memory subsystem design. Although DRAM has features such as high density and low cost, its pipelined and internal multi-bank architecture prevent commodity DRAM controllers from optimally utilizing the peak bandwidth provided by DRAM. Another serious issue is that conventional DRAM controllers cannot effectively fulfill the different memory access requirements of guaranteed bandwidth or short access latency for these heterogeneous functional units. In this thesis, we present a multi-layer memory controller for multimedia platform SoC. The proposed memory controller contains configurable, programmable and high efficient Layer 0 SDRAM memory interface socket (MIS) for designers to rapidly integrate SDRAM subsystem into their designs. Together with Layer 1 quality-aware scheduler (QAS), the memory controller also has the capability to provide quality-of-service including minimum access latencies and fine grained bandwidth allocation for heterogeneous control and computing functional units in SoC designs. Moreover, Layer 2 built-in address generator (BAG) designed for multimedia processing units can effectively reduce the address bus traffic and therefore further increase the on-chip-bus efficiency. Besides, the well-partitioned multi-layer architecture gives high flexibility to designers to adopt the most proper layers for various applications. Experimental results of a STB emulation system show that the access latency of the latency-sensitive data flow can be effectively reduced by 37%~65% compared to fixed-priority and round-robin controllers. Moreover, bandwidth allocated to each bandwidth-sensitive data flow is precisely guaranteed in all of the simulated STB events.