適用於視訊應用的智慧型記憶體控制器設計

Abstract

隨著超大型積體電路製程快速的進步，愈來愈多的元件可以輕易整合進單晶片系統。對於這些需要高度運算能力的系統來說，記憶體子系統，特別是外部動態隨機存取記憶體的頻寬跟功率消耗，是一個需要優先評估及最佳化的重點。這對一個晶片是否成功來說很重要。

在這篇論文中，我們考慮動態隨機存取記憶體的頻寬和功率消耗，以及傳輸等待時間，然後提出一個智慧型記憶體控制器設計。這個設計是利用我們自製的可設定多媒體平台模擬器來評估及開發。

對於最複雜的視訊電話模擬設定來說，我們提出幾種技巧來達到高度平均記憶體頻寬使用率。首先，我們使用記憶體同步定址來提高頻寬使用率同時降低傳輸等待時間。接著，根據視訊電話傳輸資料的特性，我們提出一種「改良式先到先處理」的排程方法。這個方法可以增加頻寬使用率同時降低記憶體功率消耗。最後，我們使用「等待時間重於指令種類」的記憶體指令排程方式來隱藏記憶體運作等待時間。如此，開發出的記憶體控制器改善平均頻寬使用率從40%到72%，並需要約485毫瓦的功率消耗。如果我們以降低記憶體功率消耗為主要考量，在滿足時間的限制條件下，我們提出另外一種設計可以節省26%的功率消耗。

我們將提出的技巧實際設計成硬體。在0.18微米的互補式金氧半導體製程下，我們的設計需要47.6K個邏輯閘並可達到166 百萬赫茲的運作頻率。

With the rapid progress of VLSI process, more and more components are easily to be integrated into one System-on-Chip. For such system with high computational power, the memory subsystem, especially the bandwidth and power consumption of external DRAM, is one of major issues that have to be evaluated and optimized first for the chip success.

In this thesis, we propose a smart memory controller design which takes DRAM bandwidth, transaction latency, and DRAM power consumption into consideration. This design is developed and evaluated by a configurable multimedia platform simulator.

For the most complex video phone scenario, we propose several techniques to achieve high average DRAM bandwidth utilization. First, we adopt the bank-interleaving support to increase the bandwidth utilization while reduce the transaction latency. Second, according to the scenario characteristics, we propose MFIFS (Modified First In First Serve) as the transaction scheduling policy. It can increase bandwidth utilization while reduce DRAM power consumption. Third, we use LTOT (Lasted Time Over Type) as the DRAM command scheduling policy to hide DRAM operation latencies. Thus, the resulted memory controller improves average bandwidth utilization from 40% to 72% with estimated 485 mW DRAM power consumption for the video phone scenario. If the design has to minimize DRAM power consumption while still meet timing constraints, another proposed memory controller can save up to 26% of power.

The proposed techniques are implemented into hardware. The implementation uses 0.18 μm CMOS process with 47.6K gates and achieves 166 MHz operating frequency.