視訊晶片中界面模組之設計與實現

Abstract

在多媒體應用中，視訊晶片是不可或缺的元件之一，依功能大致可分：壓 縮和解壓縮晶片、數位影像處理晶片、及電腦顯像晶片。而這些晶片在一 般工作模式下，皆需透過界面來與外部系統聯繫，如主處理器借由主界面 來執行指令、視訊晶片透過記憶體界面來存取記憶體資料、並由影像界面 來輸出處理後資料。因此，如何設計各個界面模組，且有良好之協調，為 研究此領域者基本但重要之課題。本篇論文除研究與實現此三個界面模組 ，並提出一個記憶體管理方法及緩衝器控制與設計，來解決記憶體頻寬有 限的問題。主界面包含一個電腦標準匯流之解碼器和寫入緩衝器，解碼器 能使本視訊晶片在個人電腦上實際運作，而寫入緩衝器則能增加主處理器 之效率。記憶體界面配合記憶體管理方法及資料緩衝器來產生外部記憶體 和內部界面間的控制訊號。緩衝器模組內包含兩個的指標，借由這兩個指 標，發出對記憶體存取的訊號，而記憶體界面一接受這些訊號，即依可設 定的優先順序決定誰能存取記憶體。影像界面包含一個陰極射線管控制器 及影像輸出單元，陰極射線管控制器產生電腦顯示器所需的同步控制訊號 ，而影像輸出單元將從記憶體讀取的資料處理後輸出。 In multimedia applications, the video chip is a necessary component. Based on various functions, the video chips can be classified into three groups : codec, video processor, and computer display chips. These chips can interact with external components by some interfaces. For example, the host processor can control the chip by host interface, and this chip can access memory data by memory interface, and then output processed data to display by video interface. Therefore, it is a fundamental but important job how to design and control these modules. In this thesis, besides the modules, we propose a scheme of memory management and buffer control to overcome the problem of memory bandwidth. The host interface includes a bus decoder and a write buffer. The decoder can be operated on PC system, and the write buffer increases the performance of host processor. The memory interface in conjunction with proposed scheme generates control signals and determined the memory arbitration according to two flags issued by the internal buffer modules. The video interface includes a CRT controller and a display unit. The CRT controller will generate synchronization signals for monitor, and that unit will retrieve data from memory and then send out for display.