適用於視訊處理之晶片內建記憶模組設計

Abstract

視訊處理晶片中經常需要快速的內建記憶體，以提供足夠的頻寬給平行的 資料路徑。利用視訊處理演算法之特性，兩個新穎的內建記憶器設計被提 出及實作。同線多重存取技術具備在一個存取週期內完成多個存取的特 性, 此技術表現出多埠記憶體能力，卻只用單埠記憶細胞之硬體和存取時 間，避免多埠記憶器的大面積、記憶細胞之不穩定性及較慢速度之缺點。 此技術用於雙埠所需面積為雙埠記憶體之62.24％，比單埠多7.6％(對大 小為2Kx8)。塊存取技術結合位址解碼器和產生器達成快速定址能力，塊 存取技術可提高速度百分之二十六(對記憶器大小為8Kb (256Wx32B))。雖 然此二種設計表現出偏好性存取之限制，但是不失一般性，因為視訊處理 演算法具有高度之平行性和較低之依賴性。各項內建記憶體之參數，都被 分析以找出各自的優缺點。一個可產生同步單、雙、三埠之記憶體產生器 以TSMC 0.8um SPDM CMOS技術發展出來，最大組態可達512Words x 32 bits。所產生之16Kb三埠記憶體存取時間為5.6ns。一大小為6634.8um x5068.8um、包含各項設計選擇的測試晶片也發展出來，送交晶片設計中 心製作。 Video signal processing chips often require fast embedded memory to provide sufficient bandwidth to parallel data path. By taking advantages of the features of video signal processing, two novel embedded memory designs are proposed and implemented for video signal processing. Concurrent line access performs multiport memory capability with single port cell cost and access time. It avoids the cell stability problem, larger area and access time overhead of multiport memories. Our design for dual ports uses 62.24% area of dual ports memory and 7.6% larger than single port memory for 2Kx8 size. Block access mode provides fast addressing by combining address decoders and generators. The access time of block access mode is 26% faster than conventional scheme for size 256wx32b. Although the two fast modes exhibit some restriction of prefer -access-order, the design is no loss of generality because algorithms of video signal processing possess high data parallelism and less dependency. A flexible memory generator that produces is developed using TSMC 0.8um SPDM CMOS technology. The access time of generated three-ports RAM is 5.6ns for 16Kb size. A test chip has also been developed and fabricated through CIC.