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dc.contributor.authorWang, CYen_US
dc.contributor.authorYang, YCen_US
dc.contributor.authorJon, JYen_US
dc.date.accessioned2014-12-08T15:26:21Z-
dc.date.available2014-12-08T15:26:21Z-
dc.date.issued2003en_US
dc.identifier.isbn0-7803-7765-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/18714-
dc.description.abstractThis paper presents an effective multiplier synthesis algorithm for cell-based multipliers. By using a novel tree generation algorithm with timing consideration for each vertical compressor slice(VCS), our synthesizer generates multipliers automatically with very promising results.en_US
dc.language.isoen_USen_US
dc.titleAn effective physical synthesis technique for multiplieren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage192en_US
dc.citation.epage195en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000189391000050-
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