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dc.contributor.authorLin, YDen_US
dc.contributor.authorLin, YNen_US
dc.contributor.authorYang, SCen_US
dc.contributor.authorLin, YSen_US
dc.date.accessioned2014-12-08T15:26:25Z-
dc.date.available2014-12-08T15:26:25Z-
dc.date.issued2002en_US
dc.identifier.isbn0-7695-1650-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/18756-
dc.description.abstractNetwork processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the data-plane processing of network services. This work, rather than proposing new algorithms, illustrates the process of and examines the performance issues in, prototyping a DiffServ edge router with IXP1200. The external benchmarks reveal that though the system can scale to wire-speed of 1.8Gbps in simple IP forwarding, the throughput declines to 180Mbpssimilar to290Mbps when DiffServ is performed due to the double bottlenecks of SRAM and microengines. Through internal benchmarks, the performance bottleneck was found to be able to shift from one place to another given different network services and algorithms. Most of the result reported here shall remain the same for other NPs since they have similar architectures and components.en_US
dc.language.isoen_USen_US
dc.titleDiffServ over network processors: Implementation and evaluationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalHOT INTERCONNECTS 10en_US
dc.citation.spage121en_US
dc.citation.epage126en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000178015100016-
Appears in Collections:Conferences Paper