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dc.contributor.authorChung, SSen_US
dc.contributor.authorLo, DKen_US
dc.contributor.authorYang, JJen_US
dc.contributor.authorLin, TCen_US
dc.date.accessioned2014-12-08T15:26:27Z-
dc.date.available2014-12-08T15:26:27Z-
dc.date.issued2002en_US
dc.identifier.isbn0-7803-7462-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/18773-
dc.description.abstractAs gate oxide thickness reduces, previous reported methods can not work well for very thin gate oxide devices as a result of the measured leakage current through the gate oxide. For the first time, a novel Low gate Leakage Gate-Diode (L-2-GD) method has been developed for the interface characterization of MOSFET devices with gate oxide in the direct tunneling regime. Three-peak experimental results, as seen from DCIV measurement, can be easily obtained from this L-2-GD method. This method has been demonstrated successfully for the ultra-thin (12-20Angstrom) gate oxide device. Also, by using this new technique, the localized oxide damage due to NBTI or HC (Hot Carrier) stress effect can be identified simply from the measured drain currents. Therefore, this L-2-GD technique is well suited for the characterization of very thin gate oxide reliabilities, and in particular for the nano-scale CMOS devices.en_US
dc.language.isoen_USen_US
dc.titleLocalization of NBTI-induced oxide damage in direct tunneling regime gate oxide pMOSFET using a novel low gate-leakage gated-diode (L-2-GD) methoden_US
dc.typeProceedings Paperen_US
dc.identifier.journalINTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGESTen_US
dc.citation.spage513en_US
dc.citation.epage516en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000185143400118-
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