利用閘二極體量測法評估雙閘極金氧半電晶體的熱載子和負偏壓溫度可靠性

Abstract

在探討金氧半元件的熱載子效應上，閘二極體（Gated-Diode）電流量測法是廣被研究的分析技術，原理是利用汲極-基極所形成的接面二極體，其產生和複合電流是閘極偏壓和界面陷阱（interface state）的函數，我們可以結合二維元件數值模擬，來偵測界面陷阱的空間分布。此外，直流電流電壓量測法（DCIV）亦是評估熱載子效應的有效方法，它是利用閘極偏壓來調節表面電位，靠著元件內部寄生的BJT結構，由基極端量測出不同的複合電流，如此就可偵測由於熱載子效應所產生的氧化層電荷（oxide charge）和界面陷阱的密度。在本論文中，我們首次深入比較直流電流電壓量測法和閘二極體量測法間的差異。我們發現，這兩個量測方法將會測得相同的複合電流，差異僅在於有無二極體的順向擴散電流。 隨著元件通道長度持續地縮減，為了維持良好的短通道效應和驅動電流能力，閘極氧化層厚度亦要跟著縮減。當閘極氧化層縮減到30A以下時，直接穿遂電流(direct tunneling current)就會發生。在直流電流電壓量法時，原本在基極端要量得的複合電流將會被從基極到閘極的直接穿遂電流給蓋過。在閘二極體量測法方面，汲極端所量測出來的複合電流也會受到從閘極流到汲極的邊緣穿遂電流影響。因此我們利用兩者的優點提出一套新的量測方法，也就是利用DCIV的順向偏壓(>|0.3|V)以及閘極二極體量測法的結構來做評估。利用這個方法，可以很容易的應用在一般生產的測試元件上面。此外，稍微加大汲極順向二極體偏壓時，不但可以降低由於汲極和閘極之間重疊區的電場 (邊緣穿遂電流也因此下降) ，而且也可讓複合電流變得較大而較不受穿遂電流的影響。在此，我們證明此方法至少可以用於閘氧化層厚度為12Å 的p 通道金氧半電晶體氧化層的傷害分析。 最後，我們將利用上述的新方法針對在n型金氧半電晶體以及p型金氧半電晶體的熱載子效應和負偏壓溫度效應進行研究。在基極熱載子偏壓測試方面，可以經由這新的閘二極體電流的圖形來觀察到其最大的傷害量將會發生在整個通道區域。在通道熱載子偏壓測試方面，吾人也可以藉由從閘二極體電流的圖形發現到其最大傷害量將發生在靠近汲極的區域，而且發現到不論是n-MOSFET或是p-MOSFET，其最大熱載子傷害量將發生在Vg=Vd的情況。而在負溫度偏壓效應實驗方面，我們也可以發現到在通道區域有大量的界面陷阱產生產生在通道邊緣處。此外，我們也針對p型金氧半電晶體在高溫下進行Vg=Vd退化實驗，結果發現熱載子效應和負溫度偏壓效應一起加強了通道邊緣的傷害量。

Recently, the gated-diode (GD) drain current measurement has been widely used to characterize hot-carrier degradation in MOSFET’s. The generation/recombination current in the drain-to-well diode as a function of the gate voltage, combined with two-dimensional numerical simulation, provides a sensitive tool for detecting the spatial distribution and density of interface defects. In addition, the DCIV measurement is also one of the most popular methods dealing with the hot carrier induced degradations in MOSFET’s. It uses gate terminal voltage, VG, to modulate the surface potential, from which, the parasitic BJT can measure different recombination currents from base terminal. In this study, for the first time, we have compared the difference between the DCIV and the gated-diode measurements. We found that these two methods monitored the same incremental recombination current induced by the oxide damage. The only difference is their forward diffusion current value. As device channel length is continuously scaled down, the gate oxide thickness is also scaled down to maintain good short channel effect and driving current. When the gate oxide thickness is scaled down below 30Å, direct tunneling current occurs. In the DCIV method, the recombination current from the base terminal will be overwhelmed by the direct tunneling current from the base terminal to the gate terminal. On the other hand, the drain current will be affected by the drain edge tunneling current in gated-diode measurements. In this study, we combine the advantages of both GD and DCIV methods to propose a new measurement method. The new method uses the strategy of forward bias in DCIV and a gated-diode configuration. This new measurement approach is superior to the typical DCIV method. Besides, in the experimental setup of this new method, the electrical field of the overlap region will be smaller and the recombination current will be easier to detect than the gate tunneling current by increasing the forward pn junction bias. It was shown that the new measurement is able to evaluate the oxide damage in pMOSFET’s with gate oxide thickness as thin as 12Å. We have applied the new GD measurement to study the hot carrier degradation in nMOSFET’s and pMOSFET’s. For substrate hot carrier stress, we can directly observe from the gated-diode current shape that most of the degradation occurs in the whole channel region. For channel hot carrier stress, we can also directly find from the gated-diode line shape that the worst degradation occurs near the drain side region. For both nMOSFET’s and pMOSFET’s under hot carrier stress, the most serious damage happens at Vg = Vd stress condition. In NBTI experiments for stressing pMOSFET at Vg = Vd and high temperature, we also found that large interface states were generated near the channel edge region. Both hot carrier and NBTI effect result in the channel edge damage.