完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chung, SS | en_US |
dc.contributor.author | Lo, DK | en_US |
dc.contributor.author | Yang, JJ | en_US |
dc.contributor.author | Lin, TC | en_US |
dc.date.accessioned | 2014-12-08T15:26:27Z | - |
dc.date.available | 2014-12-08T15:26:27Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.isbn | 0-7803-7462-2 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18773 | - |
dc.description.abstract | As gate oxide thickness reduces, previous reported methods can not work well for very thin gate oxide devices as a result of the measured leakage current through the gate oxide. For the first time, a novel Low gate Leakage Gate-Diode (L-2-GD) method has been developed for the interface characterization of MOSFET devices with gate oxide in the direct tunneling regime. Three-peak experimental results, as seen from DCIV measurement, can be easily obtained from this L-2-GD method. This method has been demonstrated successfully for the ultra-thin (12-20Angstrom) gate oxide device. Also, by using this new technique, the localized oxide damage due to NBTI or HC (Hot Carrier) stress effect can be identified simply from the measured drain currents. Therefore, this L-2-GD technique is well suited for the characterization of very thin gate oxide reliabilities, and in particular for the nano-scale CMOS devices. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Localization of NBTI-induced oxide damage in direct tunneling regime gate oxide pMOSFET using a novel low gate-leakage gated-diode (L-2-GD) method | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST | en_US |
dc.citation.spage | 513 | en_US |
dc.citation.epage | 516 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000185143400118 | - |
顯示於類別: | 會議論文 |