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dc.contributor.authorChung, SSen_US
dc.contributor.authorChen, SJen_US
dc.contributor.authorYang, CKen_US
dc.contributor.authorCheng, SMen_US
dc.contributor.authorLin, SHen_US
dc.contributor.authorSheng, YCen_US
dc.contributor.authorLin, HSen_US
dc.contributor.authorHung, KTen_US
dc.contributor.authorWu, DYen_US
dc.contributor.authorYew, TRen_US
dc.contributor.authorChien, SCen_US
dc.contributor.authorLiou, FTen_US
dc.contributor.authorWen, Fen_US
dc.date.accessioned2014-12-08T15:26:32Z-
dc.date.available2014-12-08T15:26:32Z-
dc.date.issued2002en_US
dc.identifier.isbn0-7803-7312-Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/18838-
dc.identifier.urihttp://dx.doi.org/10.1109/VLSIT.2002.1015394en_US
dc.description.abstractFor the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has, been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.en_US
dc.language.isoen_USen_US
dc.titleA novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxideen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/VLSIT.2002.1015394en_US
dc.identifier.journal2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERSen_US
dc.citation.spage74en_US
dc.citation.epage75en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000176856300028-
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