深次微米與奈米金氧半元件氧化層界面與製程導致元件可靠性的探討

Abstract

近年來，電荷幫浦法已被廣泛的應用於分析元件熱載子可靠性問題及半導體界面缺陷。在本論文中，我們將運用此一方法研究深次微米及奈米尺度互補式金氧半元件(CMOS Device)熱載子效應及製程所導致元件可靠性等問題。同時，吾人將開發一套適用於現在及未來奈米級元件界面缺陷分析之新式電荷幫浦技術。 首先，由於次微米(採用LDD結構設計)及深次微米(採用S/D 延伸結構設計)n型元件中，因汲極結構的不同，熱載子效應將會引發不同程度之汲極電流退化。其退化情形將隨著閘氧化層厚度改變及元件汲極結構不同，而呈現不規則的退化情形。迄今，尚無一個適切的方法可以同時解釋發生在這兩個世代的元件可靠性。因此，在本研究中吾人將提出一個新的熱載子可靠性的評測方式，來解釋其元件電流退化的情形。吾人利用有效通道長度中熱載子所產生的界面缺陷(Nit)量，來取代傳統採以基極電流(IB)、衝撞游離化比率((IB/ID)、或是平均/最大界面缺陷((Nit)等為可靠性的指標。經由本研究的驗證，此方法可以準確的評估這兩世代元件熱載子可靠性退化情形。 另一方面，以淺溝狀(STI)隔離法取代區域化氧化隔離法(LOCOS)已成為當代之隔離技術之主流。然而，在採用淺溝狀隔離法的元件技術中，卻發現當通道寬度縮短會造成極其嚴重的可靠性問題。在本研究中，我們以一個新的退化模型及機制來解釋與通道寬度有關之元件退化效應。其中，在n型元件中，吾人提出利用有效界面缺陷(effective Nit)來解釋元件之退化﹔在p型元件中，吾人提出利用通道長度縮短(channel-shortening)效應來解釋元件之退化。這兩種傷害的發生，都與淺溝狀隔離法所導致的機械應力傷害有莫大的關聯。 再者，在電漿蝕刻的過程中，電漿與矽晶圓表面反應，會影響到閘氧化層品質、元件可靠性、及晶圓製作的均勻度，另外，會引發兩種廣為人知的電漿蝕刻傷害- 其一為發生於氧化層及通道區域之電漿充放電傷害﹔另一為發生於閘極邊緣區域之電漿邊緣傷害。本研究則利用電荷幫浦法，來研究電漿蝕刻傷害所增強的熱載子退化現象。同時，吾人提出一個三階段的電漿傷害退化機制，用來解釋發生於n型及p型元件中電漿傷害所增強的退化現象。 最後，製程推進到奈米(sub-100nm)元件世代，元件的設計面臨到諸多物理的極限- 諸如，穿隧電流及量子效應已大到足以影響元件基本電性。這使得奈米元件的電性(尤其是在閘極氧化層品質及元件可靠性)的分析變的越趨困難。在此，吾人開發出一個新的低漏電流電荷幫浦法，它可以分析超小尺寸、超薄氧化層元件中之界面缺陷。即使當閘氧化層厚度微縮到僅僅只有1nm，此法依然可行。而附帶一提的，此法亦可用之於計算奈米元件之有效通道長度，亦可堪稱為目前世界上可合理計算出最小有效通道長度的方法。 簡而言之，本論文成功的利用電荷幫浦法於各種熱載子及製程上所導致元件可靠性問題的探討。同時，亦針對熱載子效應、淺溝狀隔離之機械應力傷害、電漿蝕刻傷害增強的退化進行研究，並提出其元件機制及物理模型。此外，亦針對具穿隧氧化層之奈米元件，提出一個新的低漏電之電荷幫浦法，用來分析超薄氧化層製程品質及其界面缺陷。相信此一新開發之電荷幫浦法，將是分析下一世代奈米元件特性最有效的工具。

The charge pumping (CP) technique has been widely used for the characterization of hot carrier (HC) reliability and the evaluation of semiconductor interface. The objective of this dissertation is to employ this CP technique for investigating the hot carrier induced and process-induced device reliabilities for device dimensions from deep-submicron to nanometer scale. In addition, a more sophisticated CP technique will be developed for the characterization of nanometer CMOS devices. First of all, since submicron (with LDD) and deep-submicron (with S/D extension) nMOSFET’s have different drain structures, it exhibits different mechanisms of drain current degradation. There exists an ambiguity that drain current degradation depends not only on gate oxide thickness but also on device drain structure. No definite method can provide an adequate solution for these two generations of devices. In this work, a new criterion for HC reliability evaluation has been proposed as a good monitor for the drain current degradation. This monitor uses total values of interface traps generated inside effective channel length, instead of the commonly used substrate current (IB), impact ionization rate (ID/IB), or peak/average values of interface traps. The approach has been successfully demonstrated to be valid for two generations of submicron (with LDD structure) and deep-submicron (with S/D extension structure) nMOSFET’s. On the other hand, the shallow-trench-isolation (STI) has become the main isolation technique to replace the local oxidation of Si (LOCOS) isolation. While, the STI CMOS devices exhibit severe degradation after hot-carrier stress with a reducing channel width. In this work, new degradation models and mechanisms has been developed to explain the width dependent degradation, in which the effective interface trap generation for nMOSFET’s and channel-shortening length for pMOSFET’s have been used as good monitors. Both HC effects in n- and pMOSFET’s are found to be strongly related to the mechanical stress on the border of the trench. Furthermore, plasma interaction with the silicon (Si) wafer during the plasma etching process of MOSFET has been known to produce serious damage, which affects the oxide quality, device reliability and wafer uniformity. There are two types of damage induced by plasma etching process- plasma-charging damage generated in the gate oxide and channel region, and plasma edge damage generated near the gate edge. This study will provide a CP profiling technique to evaluate the enhanced HC effect by the plasma-charging. In the mean time, a new three-phase plasma damage mechanism has also been proposed to clarify the enhanced degradation for both n- and pMOSFET’s Finally, in the era of sub-100nm manufacturing technique, it has reached the fundamental limits for device scaling, such as direct tunneling leakage and quantum effect. This makes the analysis of electrical characteristics in a nano-scaled device more difficult, especially the monitor of oxide quality and the evaluation of device reliability. In this study, we have also developed a new low leakage CP technique for interface trap characterization of very-short dimension and ultra-thin gate oxide devices. Even for a gate oxide thickness down to the 1nm range, this CP technique will still be valid. Moreover, this technique can also be used to calculate the effective channel length in a sub-100nm device, which is the smallest dimension of the length extraction method up-to-date. In short, this dissertation has successfully employed the CP technique to investigate the hot carrier induced and process-induced device reliabilities. Device mechanism and physical model have been well developed for the studies of the HC effect, the STI induced mechanism stress, and the plasma damage enhanced degradation. Again, a new low leakage CP method has been provided for the sub-100nm device with gate oxide in the range of direct tunneling regime. This newly developed CP technique is believed to be a very powerful tool for the characterization of next generation nanometer CMOS devices.