完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, CY | en_US |
dc.contributor.author | Wang, WC | en_US |
dc.contributor.author | Chen, TM | en_US |
dc.date.accessioned | 2014-12-08T15:26:32Z | - |
dc.date.available | 2014-12-08T15:26:32Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.isbn | 0-7803-7690-0 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18843 | - |
dc.description.abstract | This work describes a novel common-made signal rejection method for power amplifiers. A power amplifier with standard 1P5M 0.25mum CMOS technology was simulated and analyzed. This common-mode signal cancellation method makes the performance, in terms of output power and efficiency of the power amplifier, more immune to input common-mode signals than conventional power amplifiers. Simulated results indicate that this fully balanced differential power amplifier yields 24dBm output power at 2.45GHz, from a 3.3V power supply. The simulated drain efficiency is 33.21%, and the overall power-added efficiency is 32.84%. The power amplifier is highly linear. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A new high-performance CMOS GHZ power amplifier design with common-mode signal cancellation technique | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | en_US |
dc.citation.spage | 395 | en_US |
dc.citation.epage | 398 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000181146500079 | - |
顯示於類別: | 會議論文 |