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dc.contributor.authorWu, CYen_US
dc.contributor.authorWang, WCen_US
dc.contributor.authorChen, TMen_US
dc.date.accessioned2014-12-08T15:26:32Z-
dc.date.available2014-12-08T15:26:32Z-
dc.date.issued2002en_US
dc.identifier.isbn0-7803-7690-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/18843-
dc.description.abstractThis work describes a novel common-made signal rejection method for power amplifiers. A power amplifier with standard 1P5M 0.25mum CMOS technology was simulated and analyzed. This common-mode signal cancellation method makes the performance, in terms of output power and efficiency of the power amplifier, more immune to input common-mode signals than conventional power amplifiers. Simulated results indicate that this fully balanced differential power amplifier yields 24dBm output power at 2.45GHz, from a 3.3V power supply. The simulated drain efficiency is 33.21%, and the overall power-added efficiency is 32.84%. The power amplifier is highly linear.en_US
dc.language.isoen_USen_US
dc.titleA new high-performance CMOS GHZ power amplifier design with common-mode signal cancellation techniqueen_US
dc.typeProceedings Paperen_US
dc.identifier.journalAPCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGSen_US
dc.citation.spage395en_US
dc.citation.epage398en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000181146500079-
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