ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins

Abstract

This paper reports a real case for ESD level improvement on a CMOS IC product with multiple separated power pins. After ESD stress, the internal damage has been found and located at the interface circuit connecting different circuit blocks with different power supplies. Some ESD designs are implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp NMOS with a channel width of 10 mum between the interface node and ground line, the HBM ESD level of this IC product can be improved from the original 0.5 kV to 3 kV. By connecting the separated VSS power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the second version IC product with 12 separated power supplies pairs can be significantly improved from the original 1 kV up to > 5 kV, without noise coupling issue.