A two-step A/D converter in digital CMOS processes

Abstract

This paper describes a 3V 8-bit 50MSPS two-step analog-to-digital converter implemented in a 0.35mum 1P4M logic CMOS process. A PMOS biased in accumulation mode was used as a coupling capacitor in this ADC, so that the more expensive mixed mode process with double poly or MIM capacitors can be avoided. A modified switch box which greatly reduces the number of switches needed was also presented in this paper. The modified switch box can reduce the capacitance loading effect, of the resistor ladder DAC (R-DAC) and thus making the settling time of the DAC faster. The ADC occupies a die area of 0.38mm(2) (450mum*850mum) and dissipates 64mW at 50MHz clock rate with 3V single supply voltage. The FFT simulation result shows that the SNDR is 48.18dB at 5MHz input frequency and 50MSPS conversion rate and the static simulation shows that the max. INL/DNL is less than 0.5LSB/0.5LSB.