完整後設資料紀錄
DC 欄位語言
dc.contributor.authorTu, SWen_US
dc.contributor.authorShen, WZen_US
dc.contributor.authorChang, YWen_US
dc.contributor.authorChen, TCen_US
dc.date.accessioned2014-12-08T15:26:37Z-
dc.date.available2014-12-08T15:26:37Z-
dc.date.issued2002en_US
dc.identifier.isbn0-7803-7448-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/18914-
dc.description.abstractAs the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable. to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [11] is within 10% for practical cases.en_US
dc.language.isoen_USen_US
dc.titleInductance modeling for on-chip interconnectsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGSen_US
dc.citation.spage787en_US
dc.citation.epage790en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000186328000198-
顯示於類別:會議論文