標題: Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process
作者: Ker, MD
Chuang, CH
Lo, WY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2001
摘要: The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-mum salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level, The layout of I/O cell can be drawn more compactly, but still to provide deep-submicron CMOS IC's with higher ESD robustness.
URI: http://hdl.handle.net/11536/18989
ISBN: 0-7803-7057-0
期刊: ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS
起始頁: 361
結束頁: 364
顯示於類別:會議論文