標題: Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technology
作者: Ker, MD
Hong, KK
Chen, TY
Tang, H
Huang, SC
Chen, SS
Huang, CT
Wang, MC
Loh, YT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2001
摘要: Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-mum partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.
URI: http://hdl.handle.net/11536/19155
ISBN: 0-7803-6412-0
期刊: 2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS
起始頁: 41
結束頁: 44
顯示於類別:會議論文