標題: Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-bloc king mask
作者: Hsu, Hsin-Chyh
Ker, Ming-Dou
電機學院
College of Electrical and Computer Engineering
公開日期: 2006
摘要: NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 mu m/0.18 mu m) has been successfully improved from 0.5 kV (125 V) to 1.5 W (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully process compatible to general salicided CMOS processes without additional mask which is very cost-efficient for application in the IC products.
URI: http://hdl.handle.net/11536/17380
ISBN: 0-7695-2523-7
期刊: ISQED 2006: Proceedings of the 7th International Symposium on Quality Electronic Design
起始頁: 503
結束頁: 506
顯示於類別:會議論文