矽化金屬互補式金氧半導體製程之新型靜電放電防護元件

Abstract

矽化金屬沉積(salicidation)是高速互補式金氧半導體的重要製程技術，然而當此項技術應用在N型金氧半導體靜電放電保護元件上便有幾項問題存在，其中最重要的問題是N型金氧半導體元件的靜電放電保護準位過低。因為矽化金屬沉積降低汲極端的平穩電阻，使得電流集中在表面，因此產生多手指機制均勻啟動失效的問題以致於降低半導體靜電放電保護元件的ESD準位。所以如何在汲極與閘極之間形成一個適當平穩的電阻便是一個重要的課題。一般有幾種解決方式如汲極端的阻絕(salicide blocking of drain side)，使用額外的N-well平穩電阻(external N-well ballast resistors)，靜電放電防護元件植佈方法(ESD implantation methods)。然而汲極端的阻絕因為使用較多道製程，成本較高，而且存在因為蝕刻阻絕材料造成的漏電流的問題。而靜電放電保護元件植佈方法則有成本高及例如熱載子的可靠性問題，本篇論文中利用N-well電阻加在N型金氧半導體元件的汲極端，同時在N-Well電阻上方形成Field Oxide (FOX)，假性閘極 (dummy-gate)。如此分別在FOX, 假性閘極下方的N-Well電阻解決了ESD準位過低的問題，這些N型金氧半導體元件不需要額外的製程便可以被製造出來。為了與新型元件做比較，傳統的矽化金屬沉積N型金氧半導體元件，以及使用矽化金屬阻絕(salicide blocking)的元件將一併被製造，而這四種靜電放電防護N型金氧半導體元件將被提出來討論比較。

Salicidation is one of the key processes for high performance quarter-micron CMOS devices. However, several problems occur when salicide technology is implemented in ESD protection NMOS transistors. The most difficult problem is the low ESD robustness of output NMOS transistors. A salicided drain may reduce the desired ballast resistance at the drain junction, which results in current localization and failure of multi-finger uniform turn-on, thus the ESD characteristics will be degraded very much. It’s very important to make a ballast resistance between drain contact and gate edge for ESD robustness. There are several solutions such as salicide blocking of the drain area, using external N-well ballast resistors, and ESD implantation method to improve ESD robustness. However, salicide blocking method is expensive because it needs several extra process steps, and has the problem that larger leakage current can be caused by the etching of blocking materials. ESD implantation method can improve ESD robustness but it results in extra cost and other hot carriers reliability issue. In this thesis, we proposed two novel ESD protection NMOS transistors, FOX structure transistor with external N-well resistors, and dummy-gate structure transistor with external N-well resistors to form ballast resistors between drain contact and gate edge. To compare with the novel ESD protection NMOS transistors, transistors with fully-salicided and salicide blocking structures are also fabricated. Those four ESD protection NMOS transistors are compared and discussed in this thesis.