標題: UNIVERSAL TEST SET GENERATION FOR CMOS CIRCUITS
作者: CHEN, BY
LEE, CL
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: AUTOMATIC TESTING GENERATION;CMOS CIRCUITS;FUNCTIONAL TESTING;UNIVERSAL TEST SET;STUCK-OPEN FAULTS
公開日期: 1-Jun-1995
摘要: Based on the unate function theory, a universal test set for CMOS stuck-open faults in a functional block has been proposed in the existing literature. Thus, it is known that tests can be generated from the functional description and can detect all detectable stuck-open faults in any ''restricted CMOS circuit'' implementation of the function. However, the procedure to generate the tests involves a process of enumerating the expanded truth table of the function and comparing the vectors in the table. This is a very computationally demanding process. In this paper, a fast algorithm to generate the universal test set for CMOS circuits is presented. The algorithm generates the tests directly by Shannon-expanding and complementing the function, instead of the truth table enumerating. This greatly reduces the time complexity and the requirement of temporary memory. Besides, the algorithm represents the tests by ''cubes'' instead of the conventional ''patterns''. This also reduces the memory requirement for test-storing. Experimental results show that the algorithm achieves an improvement of up to six orders of magnitude in the computational efficiency and a saving of up to 2000-fold in the memory requirement for storing the tests when compared to other methods.
URI: http://dx.doi.org/10.1007/BF00996439
http://hdl.handle.net/11536/1899
ISSN: 0923-8174
DOI: 10.1007/BF00996439
期刊: JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
Volume: 6
Issue: 3
起始頁: 313
結束頁: 323
Appears in Collections:Articles