標題: | ESD test methods on integrated circuits: An overview |
作者: | Ker, MD Peng, JH Jiang, HC 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2001 |
摘要: | ESD phenomenon has become a serious problem for IC products fabricated by deep-submicron CMOS technologies. To qualify the ESD immunity of IC products, there are some test methods and standards developed by some organizations, which are ESDA, AEC, EIA/JEDEC, and MIL-STD organizations. ESD events have been classified into 4 models, which are HBM, MM, CDM, and SDM. Besides, there are 4 modes of pin combinations for ESD zapping on the IC pins, which are specified as (1) Pin-to-VSS, (2) Pin-to-VDD, (3) Pin-to-Pin, and (4) VDD-to-VSS. All the test methods are designed to evaluate the ESD immunity of IC products. The zap number, zap interval, and sample size are all well defined in the related industrial standards. This paper provides an over-view among ESD test methods on IC products. In general, the commercial IC products are requested to sustain at least 2-kV HBM, 200-V MM, and 1-kV CDM ESD stresses. |
URI: | http://hdl.handle.net/11536/19095 |
ISBN: | 0-7803-7057-0 |
期刊: | ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS |
起始頁: | 1011 |
結束頁: | 1014 |
顯示於類別: | 會議論文 |