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dc.contributor.authorKer, MDen_US
dc.contributor.authorHong, KKen_US
dc.contributor.authorChen, TYen_US
dc.contributor.authorTang, Hen_US
dc.contributor.authorHuang, SCen_US
dc.contributor.authorChen, SSen_US
dc.contributor.authorHuang, CTen_US
dc.contributor.authorWang, MCen_US
dc.contributor.authorLoh, YTen_US
dc.date.accessioned2014-12-08T15:26:55Z-
dc.date.available2014-12-08T15:26:55Z-
dc.date.issued2001en_US
dc.identifier.isbn0-7803-6412-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/19155-
dc.description.abstractElectrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-mum partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.en_US
dc.language.isoen_USen_US
dc.titleInvestigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage41en_US
dc.citation.epage44en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000169941100011-
Appears in Collections:Conferences Paper