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dc.contributor.authorLee, JSen_US
dc.contributor.authorHsu, PLen_US
dc.date.accessioned2014-12-08T15:26:59Z-
dc.date.available2014-12-08T15:26:59Z-
dc.date.issued2000en_US
dc.identifier.isbn0-7803-6563-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/19224-
dc.description.abstractRecently, methods have been proposed for obtaining the ladder logic diagram (LLD) based on the Petri net (PN). However, those resulting LLDs are usually not in compact forms. Moreover, forming the PN structures to model manufacturing processes is not straightforward. In this paper, we propose a simplified Petri net controller (SPNC) by introducing sensor states into the PN. A compact LLD can be then obtained through the token passing logic (TPL). By employing the integration definition language 0 (IDEF0) technique, we obtain the SPNC structure sequentially through diagrams. The result of an integrated IPTL (IDEF0/SPNC/TPL/LLD) algorithm, including the IDEF0, SPNC, and TPL tools, leads to the standard IEC1131-3 LLD for PLC implementation. An example of a mark stamping system is provided to illustrate the developed material The flow diagrams and information design approach.en_US
dc.language.isoen_USen_US
dc.subjectPLC (programmable logic controllers)en_US
dc.subjectDES (discrete event systems)en_US
dc.subjectSPNC (simplified Petri net controller)en_US
dc.subjectIPTL (IDEF0/SPNC/TPL/LLD)en_US
dc.subjectsequence controllersen_US
dc.titleA PLC-based design for the sequence controller in discrete event systemsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2000 IEEE INTERNATIONAL CONFERENCE ON CONTROL APPLICATIONSen_US
dc.citation.spage929en_US
dc.citation.epage934en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000166634800159-
Appears in Collections:Conferences Paper