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dc.contributor.authorChiu, JCen_US
dc.contributor.authorHuang, IHen_US
dc.contributor.authorChung, CPen_US
dc.date.accessioned2014-12-08T15:27:03Z-
dc.date.available2014-12-08T15:27:03Z-
dc.date.issued2000en_US
dc.identifier.isbn0-7695-0801-4en_US
dc.identifier.issn1063-6404en_US
dc.identifier.urihttp://hdl.handle.net/11536/19260-
dc.description.abstractThe potential performance of superscalar microprocessors can be exploited only when fed with sufficient instruction bandwidth. The front-end units, the instruction stream buffer and the fetcher, are the key elements achieving this goal. In most current processors, instruction stream buffers cannot support the instruction sequence beyond a basic block. The fetch rates ale constrained by the branch barriers. In x86 processors, the split-line instruction problem worsens this constraint. We propose a design to improve instruction stream buffer performance by coupling it with BTB to support trace prediction. According to the simulation results of such an instruction stream buffer; the maximum fetch bandwidth can reach 8.42 x86 instructions per cycle. Furthermore, we suggest that the instruction stream buffer consist of two 64-bytes entries. Compared with other existing designs, this instruction stream buffer can improve performance by 90% over current x86 processor instruction fetching on average.en_US
dc.language.isoen_USen_US
dc.subjecttrace cacheen_US
dc.subjectinstruction stream bufferen_US
dc.subjectILPen_US
dc.subjectsuperscalar processoren_US
dc.subjectx86 architectureen_US
dc.subjectmultiple instruction fetchen_US
dc.titleDesign of instruction stream buffer with trace support for x86 processorsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGSen_US
dc.citation.spage294en_US
dc.citation.epage299en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000165305100038-
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