超純量 Intel x86 相容微處理機架構之設計

Abstract

在本篇論文中，我們設計了一些提供雙管線超純量Intel x86 相容微處理機使用的架構。複雜指令集指令長度不一的問題可用一個特別的長度判斷機構來解決。這個機構可在一個時脈內判斷兩個可並行指令，所以指令擷取單元可以同時發出兩個指令到管線內執行。分歧預測單元也為雙管線超純量執行而做特別修改，不同於純量執行的預測單元，這個預測單元可以接受兩個預取指令位址並做適當的預測。此外，這單元內加了一個堆疊來處理副程式返回指令。另外，我們亦設計完成預取指令序列的架構來儲存預取的指令，有兩個序列在指令被預測分歧時相互交替提供指令。從模擬結果中顯示出，我們設計的單元可以有效地在雙管線超純量架構中執行。 這些單元可以更進一步地改善並加入新的架構技術，提供更高效能、多管線的複雜指令集處理機使用。 The target of our design is a two-issue x86 compatible superscalar processor. The variable length problem of the x86 instruction set in superscalar execution is resolved by a dedicated instruction size detector. The detector can determine two pairable instruction lengths in one cycle, so that the prefetcher can issue two instructions ultaneously. A branch prediction mechanism is also designed. This diction mechanism can accept two fetching instruction addresses and make proper prediction in one cycle. Besides, a special stack is used to keep track of the return addresses of the call-return pairs. Furthermore, a novel instruction queue unit is also accomplished. Two separate instruction queues are used to buffer the instruction stream. They switches to hold the prefetched instructions when a branch instruction predicted taken. The simulation results show that the above proposed mechanisms work effectively. These mechanisms could be further elaborated to support a high-performance multi-issue superscalar CISC processor.