標題: | Design of instruction stream buffer with trace support for x86 processors |
作者: | Chiu, JC Huang, IH Chung, CP 資訊工程學系 Department of Computer Science |
關鍵字: | trace cache;instruction stream buffer;ILP;superscalar processor;x86 architecture;multiple instruction fetch |
公開日期: | 2000 |
摘要: | The potential performance of superscalar microprocessors can be exploited only when fed with sufficient instruction bandwidth. The front-end units, the instruction stream buffer and the fetcher, are the key elements achieving this goal. In most current processors, instruction stream buffers cannot support the instruction sequence beyond a basic block. The fetch rates ale constrained by the branch barriers. In x86 processors, the split-line instruction problem worsens this constraint. We propose a design to improve instruction stream buffer performance by coupling it with BTB to support trace prediction. According to the simulation results of such an instruction stream buffer; the maximum fetch bandwidth can reach 8.42 x86 instructions per cycle. Furthermore, we suggest that the instruction stream buffer consist of two 64-bytes entries. Compared with other existing designs, this instruction stream buffer can improve performance by 90% over current x86 processor instruction fetching on average. |
URI: | http://hdl.handle.net/11536/19260 |
ISBN: | 0-7695-0801-4 |
ISSN: | 1063-6404 |
期刊: | 2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS |
起始頁: | 294 |
結束頁: | 299 |
顯示於類別: | 會議論文 |