X86超純量微處理機擷取器輔助單元

Abstract

超純量架構是新一代微處理機普遍採用以提昇效能之技術。在x86複 雜指令集相容微處理機發展至超純量架構時，受限於x86指令之不定長度 及複雜語意的特性，不易在一個時脈內如同精簡指令集微處理機般擷取多 個指令。在此論文中，我們將提出一個x86超純量微處理機擷取器輔助單 元。此單元在架構上介於記憶體與指令擷取器之間。在此單元中，有指令 流緩衝器及預先解碼器。預先解碼器最主要的目的在於標出不定長度指令 之邊界 ，以利指令擷取器在同一時脈內，能同時擷取出多個不定長度之 指令。而指令流緩衝器的目的在於能在同一個時脈內，可以提供指令擷取 器所需要的指令個數，並減少至外部記憶體擷取指令之次數。我們將針對 指令流緩衝器的寬度、深度及取代策略等方式進行討論，以找出較好的指 令流緩衝器之設計。實驗結果顯示，我們建議採用指令流緩衝器的寬度 為32位元組、深度為三個指令列項目，且使用LRU取代策略時，可以提供 足夠的指令個數至指令擷取器，而提昇微處理機之整體效能。 Superscalar processing technique is now commonly used inmicroprocessors to improve performance. For x86 architecture, because ofthe variable-length characteristic and complex semantics of instructions,it is difficult to fetch multiple instructions in one clock cycle. In this thesis, we propose a fetcher supporting unit for an x86 superscalarmicroprocessor. This unit is placed in between memory system and instruction fetcher, and it is composed of an instruction stream buffer and an instruction predecoder. The main function of the instruction predecoder is to mark the instruction boundaries. This helps the instruction fetcher to access multiple variable-length instructions in one clock cycle. The purpose of the instruction stream buffer is to provide sufficient number of instructions for the instruction fetcher in one clock cycle, reducing the necessity for frequent memory accesses. Wemeasure the instruction buffer size, depth and replacement policy to improve the instruction stream buffer design. Experimental results show that an instruction stream buffer with three entries, each being 32-bytesin length, and with LRU replacement policy can provide sufficient instruction bandwidth to the instruction fetcher and improve the overallperformance of the microprocessor.