標題: | On the study of logarithmic time parallel adders |
作者: | Yeh, WC Jen, CW 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2000 |
摘要: | This work formulates a set of equations to describe logarithmic time parallel adders. The equations can be used to explain several popular fast adder schemes and derive new adder schemes easily. It is shown that if there is an adder constructed from conditional-sum rule, then we can always obtain another adder based on carry-lookahead rule with equivalent topology and structure, and vice versa. |
URI: | http://hdl.handle.net/11536/19273 |
ISBN: | 0-7803-6488-0 |
期刊: | 2000 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION |
起始頁: | 459 |
結束頁: | 466 |
顯示於類別: | 會議論文 |