完整後設資料紀錄
DC 欄位語言
dc.contributor.authorTuan, JCen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:27:14Z-
dc.date.available2014-12-08T15:27:14Z-
dc.date.issued1998en_US
dc.identifier.isbn0-8186-8409-7en_US
dc.identifier.issn1066-1395en_US
dc.identifier.urihttp://hdl.handle.net/11536/19477-
dc.description.abstractIn this paper art architecture of full-search block matching motion estimation suitable for high qualify video is proposed. Minimum memory bandwidth is an important requirement in motion estimation architecture especially when dealing with high quality video such as large frame size video. Memory bandwidth wilt increase to an unrealistically high value without careful consideration, which no cost efficient solution can afford it, This architecture is designed for overcoming the frame memory bandwidth bottleneck by exploiting the maximum data reuse property. This is done bf setting up local memory for storing frame data. The size of local memory is also optimized to near minimum value only little overhead is introduced. Due to the reduction of memory bandwidth, the costs of frame memory modules, I/O pin count and the power consumption can be reduced but 100% hardware efficiency if still achieved Simple and regular interconnections is featured to ensure high speed operation by an efficient and distributed local memory organization.en_US
dc.language.isoen_USen_US
dc.titleAn architecture of full-search block matching for minimum memory bandwidth requirementen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSIen_US
dc.citation.spage152en_US
dc.citation.epage156en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000072704300027-
顯示於類別:會議論文