應用在全搜尋方塊比對演算法的內建式記憶體之設計與製作

Abstract

本篇論文提出一個實現半點精度全搜尋動態預估演算法的超大型積體電路 架構。此架構是建立在一可達 100% 硬體效率的半心臟陣列架構上，在不 使用太多額外面積前提下達到半點精度全搜尋動態預估。我們著眼在半點 素單元中資料的安排及處理上，如此可大量地降低緩衝記憶體的需求。為 降低外在記憶體之輸出入頻寬，整數及半點素單元中都非常需要緩衝記憶 體，因此，我們提出了為此架構而特製的記憶體。本論文所提出的架構仍 保持硬體效率達94%，而額外所需的面積不超過原有的25%。論文中亦提出 其中採用的電路技術。為增廣此記憶體之應用範圍，我們也將其發展成為 一具彈性選擇的佈局編譯器。 This thesis presents a VLSI architecture for the implementation of the half-pixel precision full-search motion estimation algorithm. The architecture is based on the semi- systolic array ME architecture which can obtain 100% efficiency in processor element arrays. We pay the emphasis on the manipulation of data for half-pel unit, which can dramatically reduce the memory demand for buffering. To reduce the I/O bandwidth of the off-chip memory, buffer memories for both integer and half-pixel unit are eagerly needed. The key component, a dedicated memory for this architecture is also presented. The proposed architecture can maintain the efficiency up to 94% cooperating with the semi- systolic array ME, and the area penalty estimated is lower than 25%. We also present the circuit techniques in the design. For larger range of applications, we also develop the memory structure to a structural layout compiler.