标题: | 应用在全搜寻方块比对演算法的内建式记忆体之设计与制作 An Embedded Dedicated Memory Design for Full Search Block Matching Algorithm |
作者: | 曾国隆 Guo-loong Tzeng 李镇宜 Chen-Yi Lee 电子研究所 |
关键字: | 动态预估; 方块比对; 半点素。;Motion Estimation; Block Matching; Half-pel. |
公开日期: | 1994 |
摘要: | 本篇论文提出一个实现半点精度全搜寻动态预估演算法的超大型积体电路 架构。此架构是建立在一可达 100% 硬体效率的半心脏阵列架构上,在不 使用太多额外面积前提下达到半点精度全搜寻动态预估。我们着眼在半点 素单元中资料的安排及处理上,如此可大量地降低缓冲记忆体的需求。为 降低外在记忆体之输出入频宽,整数及半点素单元中都非常需要缓冲记忆 体,因此,我们提出了为此架构而特制的记忆体。本论文所提出的架构仍 保持硬体效率达94%,而额外所需的面积不超过原有的25%。论文中亦提出 其中采用的电路技术。为增广此记忆体之应用范围,我们也将其发展成为 一具弹性选择的布局编译器。 This thesis presents a VLSI architecture for the implementation of the half-pixel precision full-search motion estimation algorithm. The architecture is based on the semi- systolic array ME architecture which can obtain 100% efficiency in processor element arrays. We pay the emphasis on the manipulation of data for half-pel unit, which can dramatically reduce the memory demand for buffering. To reduce the I/O bandwidth of the off-chip memory, buffer memories for both integer and half-pixel unit are eagerly needed. The key component, a dedicated memory for this architecture is also presented. The proposed architecture can maintain the efficiency up to 94% cooperating with the semi- systolic array ME, and the area penalty estimated is lower than 25%. We also present the circuit techniques in the design. For larger range of applications, we also develop the memory structure to a structural layout compiler. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT830430109 http://hdl.handle.net/11536/59303 |
显示于类别: | Thesis |