完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tuan, JC | en_US |
dc.contributor.author | Jen, CW | en_US |
dc.date.accessioned | 2014-12-08T15:27:14Z | - |
dc.date.available | 2014-12-08T15:27:14Z | - |
dc.date.issued | 1998 | en_US |
dc.identifier.isbn | 0-8186-8409-7 | en_US |
dc.identifier.issn | 1066-1395 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19477 | - |
dc.description.abstract | In this paper art architecture of full-search block matching motion estimation suitable for high qualify video is proposed. Minimum memory bandwidth is an important requirement in motion estimation architecture especially when dealing with high quality video such as large frame size video. Memory bandwidth wilt increase to an unrealistically high value without careful consideration, which no cost efficient solution can afford it, This architecture is designed for overcoming the frame memory bandwidth bottleneck by exploiting the maximum data reuse property. This is done bf setting up local memory for storing frame data. The size of local memory is also optimized to near minimum value only little overhead is introduced. Due to the reduction of memory bandwidth, the costs of frame memory modules, I/O pin count and the power consumption can be reduced but 100% hardware efficiency if still achieved Simple and regular interconnections is featured to ensure high speed operation by an efficient and distributed local memory organization. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An architecture of full-search block matching for minimum memory bandwidth requirement | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI | en_US |
dc.citation.spage | 152 | en_US |
dc.citation.epage | 156 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000072704300027 | - |
顯示於類別: | 會議論文 |