標題: | An efficient FFT algorithm based on building on-line butterfly sub-structure |
作者: | Lee, YY Lo, PC 電控工程研究所 Institute of Electrical and Control Engineering |
公開日期: | 1998 |
摘要: | This paper presents a new method of implementing the fast Fourier transform (FFT), the "real-time FFT algorithm", which efficiently utilizes the computer time to perform the FFT computation while the data acquisition proceeds. The main idea is to build the local butterfly modules using the data points available. The algorithm is based on the decimation-in-time split-radix FFT (DIT sr-FFT) butterfly structure. The algorithm is superior to the conventional whole-block FET algorithm in synchronizing with the on-line process. The time delay is about 2/r that of the whole-block algorithm considering the FFT size N=2(r). |
URI: | http://hdl.handle.net/11536/19524 |
ISBN: | 0-7803-4325-5 |
期刊: | ICSP '98: 1998 FOURTH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, PROCEEDINGS, VOLS I AND II |
起始頁: | 97 |
結束頁: | 100 |
顯示於類別: | 會議論文 |