Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, TS | en_US |
dc.contributor.author | Jen, CW | en_US |
dc.date.accessioned | 2014-12-08T15:27:17Z | - |
dc.date.available | 2014-12-08T15:27:17Z | - |
dc.date.issued | 1998 | en_US |
dc.identifier.isbn | 0-7803-4455-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19536 | - |
dc.description.abstract | This paper presents a hardware efficient architecture for transform designs. Unlike other designs that use systolic array and memory-based design, the proposed architecture exploited the constant property of the transform coefficients as well as their numerical property. The proposed design reformulates the transform with cyclic convolution such that filter type subexpression sharing can be applied to reduce the area cost. The results show that the new designs can save up to 81% gate area cost compared with previous designs for 5-point DFT designs. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Hardware efficient transform designs with cyclic formulation and subexpression sharing | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | en_US |
dc.citation.spage | A398 | en_US |
dc.citation.epage | A401 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000075224600252 | - |
Appears in Collections: | Conferences Paper |