標題: Hardware efficient transform designs with cyclic formulation and subexpression sharing
作者: Chang, TS
Jen, CW
電機學院
電子工程學系及電子研究所
College of Electrical and Computer Engineering
Department of Electronics Engineering and Institute of Electronics
公開日期: 1998
摘要: This paper presents a hardware efficient architecture for transform designs. Unlike other designs that use systolic array and memory-based design, the proposed architecture exploited the constant property of the transform coefficients as well as their numerical property. The proposed design reformulates the transform with cyclic convolution such that filter type subexpression sharing can be applied to reduce the area cost. The results show that the new designs can save up to 81% gate area cost compared with previous designs for 5-point DFT designs.
URI: http://hdl.handle.net/11536/19536
ISBN: 0-7803-4455-3
期刊: ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6
起始頁: A398
結束頁: A401
顯示於類別:會議論文