Decoding unit with high issue rate for X86 superscalar microprocessors

Abstract

In the new generation of x86 microprocessors, superscalar techniques are used to achieve higher performance by executing multiple instructions in parallel. For compatibility and higher execution parallelism, the decoding units of these microprocessors translate the x86 instructions into primitive operations. These microprocessors translate x86 instructions by the similar rca? of merging address generating into load/store operations. In this paper, we develop a nerv translating strategy of translating isolated address generation operations. Simulation results show that, in high issue rate decoding units, translating isolated address generation operations improves the performance for 20% to 25%. Besides, we find that enhancing the store buffer with the ability of snooping result buses is important for high issue rate decoding units. Furthermore, considering the tradeoff of the hardware cast and performance, we examine the decoding rules to design a decoding unit. According to the simulation results,,ve suggest a good decoding rule suitable for current commercial programs.