標題: An X86 load/store unit with aggressive scheduling of load/store operations
作者: Hwang, HY
Shiu, RM
Shann, JJJ
資訊工程學系
Department of Computer Science
關鍵字: superscalar processor;memory access ordering;x86 microprocessor;load/store unit
公開日期: 1998
摘要: Because of register-memory instruction set architecture and limited register set, there are significant amounts of memory access instructions in x86 microprocessors. As the higher issue degree of superscalar microprocessor is provided, an aggressive scheduling policy of load/store operations becomes crucial. In this paper, we examine the scheduling policies of loads/stores on x86 superscalar microprocessors and propose a new aggressive scheduling policy called load speculation, which allows loads to precede the previous unsolved pending stores. Simulation results show that the load speculation achieves the higher performance in comparison with the traditional scheduling policies such as load bypassing and load forwarding. Furthermore, by reducing the pipeline stages, the load speculation can achieve even higher performance.
URI: http://hdl.handle.net/11536/19597
ISBN: 0-8186-8603-0
期刊: 1998 INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS, PROCEEDINGS
起始頁: 496
結束頁: 503
顯示於類別:會議論文