具有資料存取指令積極排序功能的X86資料存取單元

Abstract

超純量微處理架構被廣泛地使用在現今的微處理機設計中。在這種架 構下，多個指令可以平行執行，以提高系統的效能。因為x86指令集只提 供有限的暫存器，並且支援暫存器-記憶體的定址模式，因此程式中資料 存取指令佔有相當大的比例。為了提高x86相容微處理機的系統效能，如 何提高資料存取指令的平行度變得非常重要。在目前的超純量微處理機架 構中，資料存取單元通常採用較保守的排序方式。真實資料相依性（true data dependency）是在派發到資料快取記憶體前檢查，以提供資料擷取 指令的規避執行（bypassing）及先送執行（forwarding）。當指令派發 的並行度（degree）越高時，在x86資料存取單元中則需具備更積極的指 令排序功能。 在本篇論文中，我們所提出的資料擷取指令預測執行 模式（load speculation model）可以允許資料擷取指令在真實資料相依 性尚未檢查前，即先派發到資料快取記憶體中擷取資料。這種方法較循序 執行模式（in-order model）、規避執行模式（bypassing model）及先 送執行模式（forwarding model）有更好的效能改善，而其因真實資料相 依性所造成的額外資料擷取量卻低於5.5%。此外，亦可進一步縮短其管線 層級（pipeline stage）使系統的效能更加提高。 Superscalar microarchitecture is broadly used in the modern microprocessors to execute multiple instructions in parallel. Because of limited register set and register-memory instruction set architecture, there are significant amounts of memory access instructions in x86 microprocessors. To explore more ILP of memory access operations becomes an important issue for the design of x86 microprocessors. The design of load/store units in the existed superscalar microprocessors is always restricted on the conservative scheduling of load/store operations. True data dependency is checked before issuing to the data cache. Only load bypassing or forwarding is provided in the scheduling policy of the load/store units. As higher degrees of instruction issuing are provided, more aggressive scheduling policies for load/store operations are required. In this thesis, the proposed speculation model, which allows load operations to precede the previous unsolved pending store operations, has the best performance gain in comparison with in-order, load bypassing and forwarding models. And, the additional traffic to the datacache caused by the true data dependency is always below 5.5%. The speculation model enlarges the execution window of load/store operations and gains the profit as the window size grows. In addition, the pipeline stages of the speculation model can be further reduced to gain more performance improvement.