A fault tolerant shared memory ATM switch

Abstract

In this paper, we present a fault tolerant ATM switch based on the shared memory architecture [6]. We study first the effect of a single fault to an ATM switch. Basically, a single fault in an ATM switch results in cell mis-delivery, out-of-sequence, corruption, and/or loss. We propose to add output port address, sequence number, and CRC checking to each cell for on-line fault detection. Some single faults which cause cell loss cannot be detected without wing multiple switch copies. Therefore, we propose to we a duplex system for detecting these faults and also for fault tolerant. We then design a fault tolerant switch based on the shared memory architecture [6]. Our proposed implementation can tolerate a single fault without losing cells in most cases.