標題: | The multi-chip design of analog CMOS expandable modified Hamming neural network with on-chip learning and storage for pattern classification |
作者: | Lan, JF Wu, CY 交大名義發表 電子工程學系及電子研究所 National Chiao Tung University Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1997 |
摘要: | In this paper, a multi-chip expandable modified feedforward Hamming neural network for pattern classification is designed and implemented. In the proposed modified Hamming network, the outstar circuit is used to provide the on-chip learning capability. Moreover, the embedded ratio memory in the outstar circuit is used to store the learned pattern. The chips can be connected to form pattern, element, and pattern-and-element-mixed expansions. The experimental results have been correctly verified the operation of multi-chip expansion and classification function. The contrast enhancement characteristic of the stored pattern in the 3-chip element expansion has also been observed. |
URI: | http://hdl.handle.net/11536/19715 |
ISBN: | 0-7803-3583-X |
期刊: | ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE |
起始頁: | 565 |
結束頁: | 568 |
顯示於類別: | 會議論文 |