標題: A compiled-code parallel pattern logic simulator with inertial delay model
作者: Huang, KC
Lee, JE
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
公開日期: 1997
摘要: This gaper presents a parallel pattern compiled code logic simulator which can handle the transport delay as well as the inertial delay of the logic gate. It uses Potential-Change Frame, incorporating with inertial functions, to execute event-canceling operation for gates, thus eliminating the conventional time wheel mechanism. As a result, it can adopt the parallel pattern strategy to increase the simulation speed. Furthermore, it is a compiled code simulator, which further improves its performance. Experimental results show that it surpasses significantly over the conventional time wheel. event-driven simulator in the simulation speed. In addition, it is also found that, significant percentage (27%) of hazards should be eliminated when only the transport delay is considered in the simulation.
URI: http://hdl.handle.net/11536/19719
ISBN: 0-7803-3583-X
期刊: ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE
起始頁: 1716
結束頁: 1719
顯示於類別:會議論文