Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Liang, BS | en_US |
dc.contributor.author | Nieh, YC | en_US |
dc.contributor.author | Jen, CW | en_US |
dc.date.accessioned | 2014-12-08T15:27:27Z | - |
dc.date.available | 2014-12-08T15:27:27Z | - |
dc.date.issued | 1997 | en_US |
dc.identifier.isbn | 0-7803-3583-X | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19722 | - |
dc.description.abstract | To calculate multiple independent additions with different word-length by hardware sharing, we propose a new adder architecture in this paper, named self carry routing adder (SCRA). Multiple additions for data with different precision are usually occurring in some applications, like DDA operation in 3-D graphics rendering. By segmentation, rearrangement and dynamic carry routing, SCRA design can effectively decrease the delay time, reduce hardware area, and achieve high hardware utilization. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An area and time efficient adder for multiple additions with different word-length | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | en_US |
dc.citation.spage | 2112 | en_US |
dc.citation.epage | 2115 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1997BJ47Z00529 | - |
Appears in Collections: | Conferences Paper |