A numerical model for simulating MOSFET gate current degradation by considering the interface state generation

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Yih, CM	en_US
dc.contributor.author	Chung, SS	en_US
dc.contributor.author	Hsu, CCH	en_US
dc.date.accessioned	2014-12-08T15:27:35Z	-
dc.date.available	2014-12-08T15:27:35Z	-
dc.date.issued	1996	en_US
dc.identifier.isbn	0-7803-2745-4	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19842	-
dc.language.iso	en_US	en_US
dc.title	A numerical model for simulating MOSFET gate current degradation by considering the interface state generation	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	SISPAD '96 - 1996 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES	en_US
dc.citation.spage	115	en_US
dc.citation.epage	116	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1996BG48K00053	-
顯示於類別：	會議論文