標題: INFLUENCE OF PROCESSING PARAMETERS ON THE MICROSTRUCTURE AND ELECTRICAL-PROPERTIES OF MULTILAYER-CHIP ZNO VARISTORS
作者: LEE, YS
TSENG, TY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-四月-1995
摘要: Multilayer-chip varistors based on ZnO with lead zinc borosilicate glass instead of Bi2O3 were prepared by tape casting and green-sheet lamination processes using a non-aqueous slurry system. The influences of slurry composition and the degassing process on the microstructure and non-ohmic properties of multilayer-chip varistors were studied. The electrical properties of chip varistors can be influenced substantially by the pore defects resulting from an unsuitable slurry formulation for the tape-casting process. The sintering temperature of the chip varistors was lowered to 1100 degrees C and silver-palladium alloys were employed as internal electrodes. The non-linear coefficients of 27-32 and breakdown voltages of 7.6-24.5 V were achieved by controlling the green-sheet thickness and sintering temperatures in the present study. The Delta V-br/V-br values for the chip varistors lie within +/-10%, indicating excellent surge-withstanding capability.
URI: http://dx.doi.org/10.1007/BF00188190
http://hdl.handle.net/11536/1987
ISSN: 0957-4522
DOI: 10.1007/BF00188190
期刊: JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS
Volume: 6
Issue: 2
起始頁: 90
結束頁: 96
顯示於類別:期刊論文