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dc.contributor.authorBor, JCen_US
dc.contributor.authorWu, CYen_US
dc.date.accessioned2014-12-08T15:27:38Z-
dc.date.available2014-12-08T15:27:38Z-
dc.date.issued1996en_US
dc.identifier.isbn0-7803-3702-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/19889-
dc.description.abstractIn this paper, a CMOS VLSI design of the pulse width modulation (PWM) neural network with on-chip leaning is proposed. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits with good linearity and large dynamic range. From the measured results, the linearity of synapses versus input pulse widths can be almost kept under +/-0.2%. Also the measured results on the simple Chinese word speech classification have successfully verified the function-correctness and performance of the designed neural network.en_US
dc.language.isoen_USen_US
dc.titlePulse-width-modulation feedforward neural network design with on-chip learningen_US
dc.typeProceedings Paperen_US
dc.identifier.journalAPCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96en_US
dc.citation.spage369en_US
dc.citation.epage372en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1996BH25U00090-
Appears in Collections:Conferences Paper