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dc.contributor.authorHuang, JDen_US
dc.contributor.authorJou, JYen_US
dc.contributor.authorShen, WZen_US
dc.date.accessioned2014-12-08T15:27:41Z-
dc.date.available2014-12-08T15:27:41Z-
dc.date.issued1996en_US
dc.identifier.isbn0-8186-7597-7en_US
dc.identifier.issn1063-6757en_US
dc.identifier.urihttp://hdl.handle.net/11536/19933-
dc.description.abstractIn this paper, we propose an iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. First, it finds an area-optimized performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can provide a complete set of mapping solutions from the area-optimized one to the performance-optimize one for the given design. Furthermore, these two extreme solutions, the area-optimized one and the performance-optimized one, produced by our algorithm outperform the results of most existing algorithms. Therefore, our algorithm is very useful for the timing driven FPGA synthesis.en_US
dc.language.isoen_USen_US
dc.titleAn iterative area/performance trade-off algorithm for LUT-based FPGA technology mappingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal1996 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERSen_US
dc.citation.spage13en_US
dc.citation.epage17en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1996BG84Y00003-
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