Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC's

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Ker, MD	en_US
dc.contributor.author	Wu, CY	en_US
dc.contributor.author	Cheng, T	en_US
dc.contributor.author	Chang, HH	en_US
dc.contributor.author	Wu, MJN	en_US
dc.contributor.author	Yu, TL	en_US
dc.date.accessioned	2014-12-08T15:27:44Z	-
dc.date.available	2014-12-08T15:27:44Z	-
dc.date.issued	1995	en_US
dc.identifier.isbn	7-5053-3285-6	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19997	-
dc.language.iso	en_US	en_US
dc.title	Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC's	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF THE FOURTH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY	en_US
dc.citation.spage	A193	en_US
dc.citation.epage	A195	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1995BF21N00054	-
顯示於類別：	會議論文