A NEW GATE CURRENT SIMULATION TECHNIQUE CONSIDERING SI/SIO2 INTERFACE-TRAP GENERATION

Abstract

An efficient and accurate 2D numerical simulation technique is developed to study the hot-electron effects on short-channel n-MOSFETs. The 1D substrate injection probability used by Ning el al, has been further modified by considering the channel hot-electron-enhanced injection probability. Moreover, the hot-electron-injection-induced Si/SiO2 interface-trap generation and its effects on MOSFET drain, substrate and gate currents have also been taken into consideration. It is shown that the generated electron traps at the Si/SiO2 interface enhance both the impact ionization rate and the degradation of MOSFET characteristics but retard the injection probability of hot electrons into the gate oxide. The spatial distribution of the generated Si/SiO2 interface traps calculated by our model has been well verified by the charge pumping measurement. In addition, the simulated substrate current, gate current, and degradation of drain current are in good agreement with the experimental results of a short-channel n-MOSFET with the oxide thickness of 100 Angstrom and the effective channel length of 0.45 mu m for wide ranges of drain and gate biases.