An efficient memory architecture for motion estimation processor design

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	TZENG, EG	en_US
dc.contributor.author	LEE, CY	en_US
dc.date.accessioned	2014-12-08T15:27:47Z	-
dc.date.available	2014-12-08T15:27:47Z	-
dc.date.issued	1995	en_US
dc.identifier.isbn	0-7803-2570-2	en_US
dc.identifier.issn	0277-674X	en_US
dc.identifier.uri	http://hdl.handle.net/11536/20030	-
dc.language.iso	en_US	en_US
dc.title	An efficient memory architecture for motion estimation processor design	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	1995 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3	en_US
dc.citation.spage	712	en_US
dc.citation.epage	715	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1995BD85N00179	-
顯示於類別：	會議論文